In semiconductor industries, the production of integrated circuits (ICs) mainly includes three steps: the manufacture of a wafer, the manufacturing of the integrated circuits and the package of the integrated circuits. A bare chip is formed after the steps including wafer manufacture, circuit design, mask manufacture and wafer dicing are performed. Each bare chip formed from dicing the wafer is electrically connected to an external signal through connecting points on each bare chip, and then the bare chip is encapsulated by a molding material. The purpose of the package is to prevent the bare chip from being damaged by humidity, heat and noise signals, and to provide the bare chip with an electrically connecting medium for electrically connecting the chip to an external circuit. As a result, the package step of the integrated circuit is completed.
Refer to FIG. 1. FIG. 1 illustrates a cross-sectional view of a conventional chip package. The conventional chip package 100 comprises a package substrate 110, a chip 120, a silver epoxy 130, a plurality of wires 140 and molding glue 150. The chip 120 is deposed on a carrying surface 112 of the package substrate 110. The silver epoxy 130 is disposed between the chip 120 and the carrying surface 112 to adhere the chip 120 onto the carrying surface 112 of the package substrate 110. It is known from the illustration in FIG. 1 that the chip 120 and the package substrate 110 are electrically connected to each other by the wires 140, i.e. the chip 120 and the package substrate 110 are connected by wire bonding. The wires 150 are encapsulated and protected by the molding glue 150, wherein a portion of surfaces of the chip 120 is exposed by the molding glue 150.
However, in the wire bonding process of the conventional chip package 100, because the material of the silver epoxy 130 is softer, the spillage of the silver epoxy 130 occurs (i.e. the silver epoxy 130 oozes from the periphery of the chip 120) from the pressure resulting in the wire bonding process, thereby causing poor connections between the chip 120 and the package substrate 110. Besides, during the process when the chip 120 is deposed onto the package substrate 110, the chip 120 is easily tilted because the thickness of the silver epoxy 130 is difficult to control. As a result, the yield of the chip package process is lowered, and the reliability of the chip package cannot be effectively enhanced.